Staff Engineer – Functional Verification
Job Description
Staff Engineer – Functional Verification
A leading semiconductor company developing next-generation RISC-V SoCs and accelerators is seeking a Staff Engineer in Functional Verification to ensure their systems meet the highest performance and reliability standards. This role will interface with architecture, design, physical implementation and software teams, leveraging advanced verification methodologies and tools.
Key Responsibilities:
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Analyze system and architecture requirements to develop detailed test and coverage plans.
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Define and implement scalable verification methodologies across multiple environments.
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Develop and maintain verification environments in SystemVerilog/UVM, SystemC and C++, including stimulus, checkers, assertions, trackers and coverage.
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Execute verification plans, including design bring-up, regression testing and debugging test failures.
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Perform HW/SW co-verification and simulation, root-cause analysis and collaborate with cross-functional teams to achieve verification closure.
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Contribute to verification methodology improvements and mentor junior engineers.
Requirements:
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Master’s degree in a relevant field.
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10+ years of experience verifying complex SoCs or IP blocks.
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Expertise in SystemVerilog/UVM, SystemC/C++, constrained random verification and functional coverage.
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Experience with formal verification, UPF and HW-SW co-verification.
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Familiarity with scripting (Bash, Perl, Python) and verification management tools.
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Strong analytical, problem-solving, and debugging skills.
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Excellent English communication skills and ability to work autonomously and in multicultural teams.
Desirable:
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Firmware-based verification, metrics-driven verification, or experience with NOC, PCIe, DDR, HBM, or other standard IPs.
Why Join:
Work in a hybrid, flexible environment with a pioneering team driving next-generation AI, HPC, and edge SoC platforms, with opportunities for professional growth and competitive remuneration.